The present invention relates to bond and etchback semiconductor-on-insulator (BESOI) semiconductor processing technology and related structures.
FIG. 1 (Prior Art) is a cross-sectional diagram of a conventional complementary metal oxide semiconductor (CMOS) transistor structure 1 often used in contemporary ultra large scale integration. The diagram is simplified to better illustrate the related issues. Structure 1 includes a P-channel transistor 2 having a source region 3, a drain region 4 and a gate 5. A channel region exists between source region 3 and drain region 4. Source region 3 and drain region 4 extend into in an N-type well region 6.
The structure also includes an N-channel transistor 7 having a source region 8, a drain region 9 and a gate 10. A channel region exists between source region 8 and drain region 9. Source region 8 and drain region 9 extend into in a P-type well region 11. Well regions 6 and 11 are diffused into a bulk semiconductor substrate 12. Bulk substrate 12 in this case is monocrystalline silicon of a silicon wafer. In this example, well region 11 is reverse biased with respect to substrate 12. Each of the wells and the substrate is provided with a contact so that the wells and substrate can be maintained at the appropriate potentials. Above the upper surface 13 (sometimes called the xe2x80x9cface sidexe2x80x9d) of the semiconductor wafer are multiple interleaved layers of metallization and insulation (not shown). The metallization layers interconnect the various transistors to form a desired integrated circuit.
In MOS transistors such as the transistors of FIG. 1, switching speed is limited by the time required to charge and discharge the capacitances between device electrodes. If parasitic capacitances between the device electrodes can be reduced, then device speed can be increased. In each of the two transistors of FIG. 1, there exists a junction capacitance between the source region and the well region, a junction capacitance between the drain region and the well region, and a junction capacitance between the P-well region and the substrate. A process is desired that reduces these capacitances and therefore speeds transistor operation.
In addition to transistors 2 and 7 of FIG. 1 being slowed due to the presence of parasitic junction capacitances, the performance of transistors 2 and 7 also suffers due to a resistance existing between the well contact and the channel of each transistor. Radiation such as alpha particles can be penetrate into the semiconductor material of the transistors. Each alpha particle generates electron-hole pairs along its path as it passes into the semiconductor material of the device. If, for example, the electron-hole pairs are generated in a portion of the semiconductor material in which an electric field is present (for example, due to the reverse bias of a well-to-substrate junction), then the electrons and holes may be separated by the electric field. The resulting current is then typically drawn out of the well region through the well contact. One such alpha particular may, for example, generate one million such electron hole pairs. If the current path of the resulting current passes under the channel on its way from the well-to-substrate junction to the well contact, then a momentary voltage drop will exist across the current path due to the resistance of the well under the channel. This momentary voltage may affect the threshold voltage of the transistor or otherwise affect transistor operation.
In addition to currents flowing past the channel region of a transistor due to alpha particles, the normal switching of the transistors can also cause undesirable currents to flow in the transistor structure of FIG. 1. A first junction capacitance exists between the well region of the N-channel transistor and the substrate. A second junction capacitance exists between the substrate and the well region of the P-channel transistor. These capacitances are oriented in series with one another. Consider the situation in which the drains of the N-channel and P-channel transistors are coupled together to that the transistors form an inverter. As the transistors switch, the voltages on the drains of the transistors change, thereby causing small local changes in the voltages in the well regions. The result is current flow in a current path formed by the series coupled capacitances. This current through the well resistance, like the current due to alpha particles, may cause momentary voltage changes as the current flows through the resistance of the well region underneath a transistor channel. Such voltage fluctuations may adversely affect transistor operation.
These and other problems exist due to resistances and junction capacitances of the structure.
Using silicon-on-insulator (SOI) processing technology, transistors can be fabricated in a thin semiconductor layer that is supported and insulated from an underlying supporting substrate. In one so-called xe2x80x9cbond and etchbackxe2x80x9d SOI (BESOI) device architecture, an insulating layer is formed over a device wafer. Etch stops are formed into the surface of the device wafer. A supporting xe2x80x9chandlexe2x80x9d wafer is then bonded to the insulating layer of the device wafer, and the back side of the device wafer is thinned in a planar fashion using a thinning technique until the etch stops are reached. Chemical mechanical polishing (CMP) may be used to perform this thinning. The resulting structure is a very thin layer of the device wafer that is insulated from the underlying supporting substrate by the insulating layer. Transistors are then formed into this thin layer of the device wafer. Because the transistors do not have well regions that extend into the underlying supporting substrate, the transistors do not have the associated junction capacitances. Commonly acknowledged advantages of BESOI devices include: 1) less junction capacitance so higher speed can be achieved, 2) reduced susceptibility to problems causes by radiation such as alpha particles, and 3) better isolation between transistors and increased freedom from latchup.
Although such BESOI techniques exist, the transistors nonetheless still suffer from an amount of junction capacitance. Moreover, the resistance of the well material in the area underneath the channel is present. Current through this area can still cause voltages that have undesirable influences on transistor operation. Resistance of the transistors to single event upsets, although improved, still remains. In addition to the well contacts involving a resistance, they also occupy an amount of area on the surface SOI wafer.
An improved processing technology is desired.
A supporting structure such as a silicon wafer is wafer-bonded to the upper face side of a partially processed or fully processed device wafer. The device wafer includes a field effect MOS transistor. The field effect transistor includes a well region that extends into the substrate material of the device wafer. The source region and drain region of the field effect transistor extend at least partly into the well region.
After attachment of the supporting structure, the device wafer is thinned from the back side of the device wafer until the bottom of the well region is exposed. A well contact region is then ion implanted into the exposed bottom surface of the well region and a metal electrode is formed to make contact to the well region from the back side of the device wafer. The resulting transistor structure has a reduced amount of well-to-substrate parasitic junction capacitance because the well region to substrate junction area that would have otherwise existed on the bottom of the well region has been removed. Resistance between the well contact and the channel region of the transistor is reduced because the well contact is disposed close to the channel region directly under the gate of the transistor.
In another embodiment, the substrate region of a device wafer is thinned from the back side until the bottom of the well region is exposed. All the substrate material disposed underneath the well region is therefore removed. A subsequent etching step is then performed to etch away all remaining portions of the substrate region (for example, between transistors). The result is islands of well material. There is little or no well-to-substrate material interface because all or substantially all of the substrate material is removed. The associated parasitic well-to-substrate junction capacitance is therefore eliminated or reduced. In one embodiment, contact is made to the well regions by metal that extends down from the top of the source regions and across the bottoms of the well regions to well contact regions disposed directly underneath the gates of the transistors on the back side of the device wafer.
In another embodiment, a device wafer is thinned from the back side past the point of exposing the well region of the transistor. Rather, the device wafer is thinned from the back side until the bottoms of the source and drain regions of the transistor are reached. Only a small amount of the well region remains. This amount of well region material is disposed principally between the source region and the drain region. Accordingly, the associated source-to-well and drain-to-well junction capacitances are reduced. Contact is made to the narrow amount of remaining well material between the source region and the drain region by leaving a relatively large contact portion of the well material in contact with the narrow portion of the well material. The remaining well material therefore has a key-shaped structure. The wide part of the key-shaped structure is the contact portion. The narrow portion of the key-shaped structure is the narrow channel portion.
In one embodiment, a metal well electrode in the interconnect portion of the device wafer makes electrical connection with the key-shaped well structure via the contact portion of the key-shaped well region. The contact portion of the key-shaped well region is therefore coupled in a vertical direction to the well electrode in the overlaying interconnect portion of the device wafer.
In another embodiment, metal is deposited and patterned onto the back side of the device wafer to make a well electrode that contacts the remaining well region from the back side of the device wafer. A bias voltage is placed onto this well electrode from a source disposed on the back side of the device wafer, as opposed to being supplied from a well electrode disposed in the interconnect portion of the device wafer. By placing the well electrode on the back side of the device wafer, space on the upper device side of the device wafer that would otherwise be used for the well contact is now usable for other purposes such as, for example, achieving closer component spacing.
In another embodiment, the narrow portion of the key-shaped well structure between the source region and the drain region is thinned from the back side so that it is thinner than the adjacent source and drain regions. After thinning, the source region, drain region and thinned well material are oxidized to form a thin thermal oxide. An area of the thin thermal oxide is then removed to form a second gate contact area. Metal is then deposited on the thin thermal oxide and is patterned to form a second gate electrode. Metal of the second gate electrode makes electrical contact with the electrode of the first gate through the second gate contact region. The resulting double gate transistor structure has substantially no substrate-to-well region junction capacitance because all or substantially all of the substrate-to-well junction has been removed. The resulting double gate transistor has very little source-to-well or drain-to-well junction capacitance because the well has been thinned and patterned such that the only contact between the well material and the source and drain is in the narrow channel region between the source region and the drain region. The threshold voltage of each of the channels of the resulting double gate transistor can be adjusted to improve subthreshold leakage of the double gate transistor.
By eliminating the substrate material altogether, by reducing the size of the drain regions as compared to the source regions, and/or by placing the well electrodes and associated contacts on the back side of the device wafer, less device wafer surface area is required to fabricate the transistors of the present invention as compared to the transistors of the conventional structure of FIG. 1. Closer component spacing is therefore possible without reducing the minimum feature size achievable with the semiconductor fabrication process used and without any reduction in minimum lithography dimensions.
Other structures and methods are described in the detailed description below. This summary does not purport to define the invention. The invention is defined by the claims.